Semiconductor memory devices such as random access memory (RAM) devices typically include a number of memory cells coupled to at least one bit line. The memory cells often include at least one storage transistor, storage node, and pass gate transistor. Generally, two storage transistors are coupled between two pass gate transistors, and a bit line is coupled to each of the pass transistors. Thus, each memory cell is often located between two bit lines.
The pass gate transistors have gate electrodes which are coupled to word lines. A signal such as an address or select signal is provided on the word line associated with the memory cell to select or access a particular memory cell. Once the memory cell is selected via the word line, the memory cell can be read or written to through the pass gate transistors via the bit lines.
Semiconductor memory cells include static RAM devices (SRAMs). The memory cell of the SRAM often contains two inverters connected in anti-parallel. Basically, each cell is a flip-flop which has two stable states (e.g., a logic 1 or a logic 0). The memory cell is generally made of four or six transistors. In a four transistor SRAM cell, a first resistor is coupled in series with a first pull down (e.g., storage or drive) transistor at a first storage node, and a second resistor is coupled in series with a second pull down transistor at a second storage node. A first pass gate is coupled between a first bit line and the first storage node, and a second pass gate is coupled between a second bit line and a second storage node.
In a six transistor memory cell, the first and second resistors are replaced by first and second load transistors. The load transistors can be P-channel transistors, diodes, or depletion mode N-channel transistors or other load element. The pull down transistors and pass gate transistors for both four transistor cells and six transistor cells are often N-channel enhancement mode transistors.
As the advance of technology has increased the storage capacity of memory devices, bit lines have become longer as they connect more memory cells. The increased length of the bit line increases the capacitive and resistive effects associated with the bit line. Additionally, memory cell size has steadily decreased so more memory cells can be located on a single semiconductor substrate. The decreased memory cell size makes it more difficult for the memory cell to sink (e.g., receive) and source (e.g., supply) current as the memory cell is accessed. The current sinking and sourcing problem is enhanced by the larger capacitance and resistance associated with longer bit lines because the transmitted signal across the bit lines is dissipated across the longer length of the bit lines. For example, the memory cell must provide enough current sinking and sourcing capability to overcome the capacitance and resistance of the entire bit line before the logic level of the signal may be appropriately read from the cell or be appropriately written to the cell.
Thus, there is a need for a memory cell which has superior current sourcing and sinking characteristics. Further, there is a need for a memory cell of minimal size which can appropriately read, write, and store logic signals. Further still, there is a need for a stable memory cell of small size which is relatively immune to noise.